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features description sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 high-speed differential line receivers four- ('390), eight- ('388a), or sixteen- ('386) line receivers meet or exceed the requirements of ansi tia/eia-644 standard integrated 110- w line termination resistors on lvdt products designed for signaling rates (1) up to 630 mbps sn65 version's bus-terminal esd exceeds 15 kv operates from a single 3.3-v supply typical propagation delay time of 2.6 ns output skew 100 ps (typ) part-to-part skew is less than 1 ns lvttl levels are 5-v tolerant open-circuit fail safe flow-through pinout packaged in thin shrink small-outline package with 20-mil terminal pitch this family of four-, eight-, or sixteen-, differential line receivers (with optional integrated termination) im- plements the electrical characteristics of low-voltage differential signaling (lvds). this signaling technique lowers the output voltage levels of 5-v differential standard levels (such as eia/tia-422b) to reduce the power, increase the switching speeds, and allow operation with a 3-v supply rail. any of the eight or sixteen differential receivers provides a valid logical output state with a 100-mv differential input voltage within the input common-mode voltage range. the input common-mode voltage range allows 1 v of ground potential difference between two lvds nodes. additionally, the high-speed switching of lvds signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. the lvdt products eliminate this external resistor by integrating it with the receiver. (1) signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second) please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 1999?2004, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com 12 3 4 5 6 7 8 9 10 1 1 1213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gndv c c v c c gndena a1y a2y a3y a4y enb b1y b2y b3y b4y gnd v c c v c c gndc1y c2y c3y c4y enc d1y d2y d3y d4y end gnd v c c v c c gnd a1aa1b a2a a2b a3a a3b a4a a4b b1a b1b b2a b2b b3a b3b b4a b4b c1ac1b c2a c2b c3a c3b c4a c4b d1a d1b d2a d2b d3a d3b d4a d4b 12 3 4 5 6 7 8 1615 14 13 12 1 1 10 9 1a1b 2a 2b 3a 3b 4a 4b en1,21y 2y v c c gnd3y 4y en3,4 'l vds390, 'l vdt390 d or pw p ackage (t op view) 'l vds386, 'l vdt386 dgg p ackage (t op view) 12 3 4 5 6 7 8 9 10 1 1 1213 14 15 16 17 18 19 3837 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 gndv c c enaa1y a2y enb b1y b2y dgnd dv c c dgndc1y c2y enc d1y d2y end v c c gnd a1aa1b a2a a2b agnd b1ab1b b2a b2b agnd c1ac1b c2a c2b agnd d1ad1b d2a d2b 'l vds388a, 'l vdt388a dbt p ackage (t op view) see application section for v c c and gnd description.
description (continued) sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. the intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 w . the transmission media may be printed-circuit board traces, backplanes, or cables. the large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. when used with its companion, 8- or 16-channel driver, the sn65lvds389 or sn65lvds387, over 300 million data transfers per second in single-edge clocked systems are possible with little power. (note: the ultimate rate and distance of data transfer depends on the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.) available options temperature number of part number bus-pin esd symbolization range receivers SN65LVDS386DGG ?40 c to 85 c 16 15 kv lvds386 sn65lvdt386dgg ?40 c to 85 c 16 15 kv lvdt386 sn75lvds386dgg 0 c to 70 c 16 4 kv 75lvds386 sn75lvdt386dgg 0 c to 70 c 16 4 kv 75lvdt386 sn65lvds388adbt ?40 c to 85 c 8 15 kv lvds388a sn65lvdt388adbt ?40 c to 85 c 8 15 kv lvdt388a sn75lvds388adbt 0 c to 70 c 8 4 kv 75lvds388a sn75lvdt388adbt 0 c to 70 c 8 4 kv 75lvdt388a sn65lvds390d ?40 c to 85 c 4 15 kv lvds390 sn65lvds390pw ?40 c to 85 c 4 15 kv lvds390 sn65lvdt390d ?40 c to 85 c 4 15 kv lvdt390 sn65lvdt390pw ?40 c to 85 c 4 15 kv lvdt390 sn75lvds390d 0 c to 70 c 4 4 kv 75lvds390 sn75lvds390pw 0 c to 70 c 4 4 kv ds390 sn75lvdt390d 0 c to 70 c 4 4 kv 75lvdt390 sn75lvdt390pw 0 c to 70 c 4 4 kv dg390 2 www .ti.com
equivalent input and output schematic diagrams sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 logic diagram (positive logic) function table snx5lvd386/388a/390 and snx5lvdt386/388a/390 differential input (1) enables (1) output (1) a-b en y v id 3 100 mv h h ?100 mv < v id 100 mv h ? v id -100 mv h l x l z open h h (1) h = high level, l = low level, x = irrelevant, z = high impedance (off), ? = indeterminate 3 www .ti.com 'l vdx386 1a1b 2a 2b 3a 3b 4a 4b 1y 2y 3y4y 'l vdt386 onl y 'l vdx388a en 1a1b 2a 2b 1y 2y 'l vdt388a onl y en 'l vdx390 1a1b 2a 2b 3a 3b 4a 4b 1y 2y 3y4y 'l vdt390 onl y enen (1/4 of 'l vdx386 shown) (1/4 of 'l vdx388a shown) ('l vdx390 shown) 300 k w 300 k w v c c 7 v 7 v a input b input 7 v 400 w v c c en v c c 5 w 7 v y output 300 k w 1 10 w 'l vdt devices only
absolute maximum ratings dissipation rating table recommended operating conditions sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 over operating free-air temperature (unless otherwise noted) (1) units v cc (2) supply voltage range ?0.5 v to 4 v v i voltage range: enables or y ?0.5 v to 6 v a or b ?0.5 v to 4 v i o output current y 12 ma |v id | differential input voltage magnitude sn65lvdt' or sn75lvdt' only 1 v electrostatic discharge: see (3) sn65' (a, b, and gnd) class 3, a:15 kv, b: 400 v sn75' (a, b, and gnd) class 2, a:4 kv, b: 400 v continuous power dissipation see dissipation rating table t stg storage temperature range ?65 c to 150 c lead temperature 1,6 mm (1/16 in) from case 260 c for 10 seconds (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values, except differential i/o bus voltages, are with respect to network ground terminal. (3) tested in accordance with mil-std-883c method 3015.7. derating factor (1) t a = 70 c t a = 85 c package t a 25 c above t a = 25 c power rating power rating d 950 mw 7.6 mw/ c 608 mw 494 mw dbt 1071 mw 8.5 mw/ c 688 mw 556 mw dgg 2094 mw 16.7 mw/ c 1342 mw 1089 mw pw 774 mw 6.2 mw/ c 496 mw 402 mw (1) this is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow. min nom max unit v cc supply voltage 3 3.3 3.6 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v i o output current y ? 8 8 ma |v id | magnitude of differential input voltage 0.1 0.6 v v ic , see figure 4 common-mode input voltage v v cc ? 0.8 sn75' 0 70 c t a operating free-air temperature sn65' ?40 85 c 4 www .ti.com 2 . 4 | v i d | 2 | v i d | 2
electrical characteristics sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit v it+ positive-going differential input voltage threshold 100 mv see figure 1 and table 1 v it? negative-going differential input voltage threshold ?100 mv v oh high-level output voltage i oh = ?8 ma 2.4 3 v v ol low-level output voltage i ol = 8 ma 0.2 0.4 v 'lvdx386 50 70 'lvdx388a enabled, no load 22 40 'lvdx390 8 18 i cc supply current ma 'lvdx386 3 'lvdx388a disabled 3 'lvdx390 1.5 v i = 0 v ?13 ?20 'lvds v i = 2.4 v ?1.2 ?3 v i = 0 v, other input i i input current (a or b inputs) a ?40 open 'lvdt v i = 2.4 v, other input ?2.4 open v ia = 0 v, v ib = 0.1 v, i id differential input current |i ia - i ib | 'lvds 2 a v ia = 2.4 v, v ib = 2.3 v v ia = 0.2 v, v ib = 0 v, i id differential input current (i ia - i ib ) 'lvdt 1.5 2.2 ma v ia = 2.4 v, v ib = 2.2 v i i(off) power-off input current (a or b inputs) 'lvds v cc = 0 v, v i = 2.4 v 12 20 a i i(off) power-off input current (a or b inputs) 'lvdt v cc = 0 v, v i = 2.4 v 40 a i ih high-level input current (enables) v ih = 2 v 10 a i il low-level input current (enables) v il = 0.8 v 10 a v o = 0 v 1 i oz high-impedance output current a v o = 3.6 v 10 c in input capacitance, a or b input to gnd v id = 0.4 sin 2.5e09 t v 5 pf z (t) termination impedance v id = 0.4 sin 2.5e09 t v 88 132 w (1) all typical values are at 25 c and with a 3.3-v supply. 5 www .ti.com
switching characteristics parameter measurement information sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit t plh propagation delay time, low-to-high-level output 1 2.6 4 ns t phl propagation delay time, high-to-low-level output 1 2.5 4 ns t r output signal rise time 500 800 1200 ps t f output signal fall time see figure 2 500 800 1200 ps t sk(p) pulse skew (|t phl - t plh |) 150 600 ps t sk(o) output skew (2) 100 400 ps t sk(pp) part-to-part skew (3) 1 ns t pzh propagation delay time, high-impedance-to-high-level output 7 15 ns t pzl propagation delay time, high-impedance-to-low-level output 7 15 ns see figure 3 t phz propagation delay time, high-level-to-high-impedance output 7 15 ns t plz propagation delay time, low-level-to-high-impedance output 7 15 ns (1) all typical values are at 25 c and with a 3.3-v supply. (2) t sk(o) is the magnitude of the time difference between the t plh or t phl of all drivers of a single device with all of their inputs connected together. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits. figure 1. voltage definitions table 1. receiver minimum and maximum input threshold test voltages resulting differential resulting common- applied voltages input voltage mode input voltage v ia v ib v id v ic 1.25 v 1.15 v 100 mv 1.2 v 1.15 v 1.25 v ?100 mv 1.2 v 2.4 v 2.3 v 100 mv 2.35 v 2.3 v 2.4 v ?100 mv 2.35 v 0.1 v 0 v 100 mv 0.05 v 0 v 0.1 v ?100 mv 0.05 v 1.5 v 0.9 v 600 mv 1.2 v 0.9 v 1.5 v ?600 mv 1.2 v 2.4 v 1.8 v 600 mv 2.1 v 1.8 v 2.4 v ?600 mv 2.1 v 0.6 v 0 v 600 mv 0.3 v 0 v 0.6 v ?600 mv 0.3 v 6 www .ti.com v i b v i d v i a v i c v o ab r v i a v i b 2
sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 50 mpps, pulse width = 10 0.2 ns. c l includes instrumentation and fixture capacitance within 0,06 mm of the d.u.t. figure 2. timing test circuit and wave forms 7 www .ti.com v o h v o l 1.5 v v o v i a v i b v i d 1.4 v1 v 0.4 v 0 v 0.4 v t p h l t p l h t r t f 20% 80% v i b v i d v i a v o c l 10 pf
sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 0.5 mpps, pulse width = 500 10 ns. c l includes instrumentation and fixture capacitance within 0,06 mm of the d.u.t. figure 3. enable/disable time test circuit and wave forms 8 www .ti.com v t e s t a t p z l t p l z 2.5 v1.4 v v o l +0.5 v v o l 2 v1.4 v 0.8 v 2.5 v1 v en y v t e s t a t p z h t p h z v o h 1.4 v v o h 0.5 v 0 v 2 v1.4 v 0.8 v 0 v1.4 v en y v o c l 10 pf + 500 w 1.2 v ba en inputs v t e s t
typical characteristics sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 lvdx390 common-mode input voltage supply current vs vs differential input voltage switching frequency figure 4. figure 5. lvdx388a lvdx386 supply current supply current vs vs switching frequency switching frequency figure 6. figure 7. 9 www .ti.com f ? switching frequency ? mhz 0 100 200 300 400 500 600 0 50 100 150 200 250 300 i cc ? supply current ? ma v c c = 3.6 v v c c = 3 v v c c = 3.3 v f ? switching frequency ? mhz 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 i cc ? supply current ? ma v c c = 3.6 v v c c = 3 v v c c = 3.3 v f ? switching frequency ? mhz 0 20 40 60 80 100 120 140 0 50 100 150 200 250 300 350 i cc ? supply current ? ma v c c = 3.6 v v c c = 3 v v c c = 3.3 v |v i d | ? differential input v oltage ? v 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 max at v c c = 3 v max at v c c > 3.15 v minimum ? common-mode input v oltage ? v v ic
sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 typical characteristics (continued) high-level output voltage low-level output voltage vs vs high-level output current low-level output current figure 8. figure 9. low-to-high propagation delay time high-to-low propagation delay time vs vs free-air temperature free-air temperature figure 10. figure 11. 10 www .ti.com i o h ? high-level output current ? ma 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 v oh ? high-level output v oltage ? v i o l ? low-level output current ? ma 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 10 20 30 40 50 60 70 80 ol v ? low-level output v oltage ? v t a ? free-air t emperature ? c 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 ?50 ?30 ?10 10 30 50 70 90 v c c = 3.6 v v c c = 3 v v c c = 3.3 v t plh ? low-t o-high propagation delay t ime ? ns t a ? free-air t emperature ? c 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 ?50 ?30 ?10 10 30 50 70 90 v c c = 3.6 v v c c = 3 v v c c = 3.3 v t phl ? high-t o-low propagation delay t ime ? ns
application information analog and digital grounds/power supplies fail safe sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 figure 12. typical application schematic although it is not necessary to separate out the analog/digital supplies and grounds on the sn65lvds/t388a and sn75lvds/t388a, the pinout provides the user that option. to help minimize or perhaps eliminate switching noise being coupled between the two supplies, the user could lay out separate supply and ground planes for the designated pinout. most applications probably have all grounds connected together and all power supplies connected together. this configuration was used while characterizing and setting the data-sheet parameters. one of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. the lvds receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between ?100 mv and 100 mv, and within its recommended input common-mode voltage range. ti's lvds receiver is different in how it handles the open-input circuit situation, however. open-circuit means that there is little or no input current to the receiver from the data line itself. this could be when the driver is in a high-impedance state or the cable is disconnected. when this occurs, the lvds receiver pulls each line of the signal pair to near v cc through 300-k w resistors, as shown in figure 13. the fail-safe feature uses an and gate with input voltage thresholds at about 2.3 v to detect this condition and force the output to a high-level, regardless of the differential input voltage. 11 www .ti.com host controller tx clock l vds drivers t arget controller t arget indicates twisting of theconductors. t t t t t indicates the line terminationcircuit. host balanced interconnect power power db0 db1 db2 dbn3 t t t t dbn2 dbn1 dbn rx clock db0 db1 db2 dbn3 dbn2 dbn1 dbn l vdx368, l vdx388 l vdx388a, or l vdx390
sn65lvds386/388a/390, sn65lvdt386/388a/390 sn75lvds386/388a/390, sn75lvdt386/388a/390 slls394g ? september 1999 ? revised november 2004 application information (continued) figure 13. open-circuit fail safe of the lvds receiver it is only under these conditions that the output of the receiver is valid with less than a 100-mv differential input voltage magnitude. the presence of the termination resistor, rt, does not affect the fail-safe function as long as it is connected as shown in the figure. other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. 12 www .ti.com rt = 100 w (t yp) 300 k w 300 k w v c c v i t 2.3 v a b y
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN65LVDS386DGG active tssop dgg 64 25 tbd cu nipdau level-1-220c-unlim SN65LVDS386DGGr active tssop dgg 64 2000 tbd cu nipdau level-1-220c-unlim sn65lvds388adbt active sm8 dbt 38 50 tbd cu nipdau level-2-220c-1 year sn65lvds388adbtr active sm8 dbt 38 2000 tbd cu nipdau level-2-220c-1 year sn65lvds390d active soic d 16 40 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim sn65lvds390dr active soic d 16 2500 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim sn65lvds390pw active tssop pw 16 90 tbd cu nipdau level-1-220c-unlim sn65lvds390pwr active tssop pw 16 2000 tbd cu nipdau level-1-220c-unlim sn65lvdt386dgg active tssop dgg 64 25 tbd cu nipdau level-1-220c-unlim sn65lvdt386dggg4 preview tssop dgg 64 25 tbd call ti call ti sn65lvdt386dggr active tssop dgg 64 2000 tbd cu nipdau level-1-220c-unlim sn65lvdt388adbt active sm8 dbt 38 50 tbd cu nipdau level-2-220c-1 year sn65lvdt388adbtr active sm8 dbt 38 2000 tbd cu nipdau level-2-220c-1 year sn65lvdt390d active soic d 16 40 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim sn65lvdt390dr active soic d 16 2500 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim sn65lvdt390pw active tssop pw 16 90 tbd cu nipdau level-1-220c-unlim sn65lvdt390pwr active tssop pw 16 2000 tbd cu nipdau level-1-220c-unlim sn75lvds386dgg active tssop dgg 64 25 tbd cu nipdau level-1-220c-unlim sn75lvds386dggr active tssop dgg 64 2000 tbd cu nipdau level-1-220c-unlim sn75lvds388adbt active sm8 dbt 38 50 tbd cu nipdau level-2-220c-1 year sn75lvds388adbtr active sm8 dbt 38 2000 tbd cu nipdau level-2-220c-1 year sn75lvds390d active soic d 16 40 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim sn75lvds390dr active soic d 16 2500 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim sn75lvds390pw active tssop pw 16 90 tbd cu nipdau level-1-220c-unlim sn75lvds390pwr active tssop pw 16 2000 tbd cu nipdau level-1-220c-unlim sn75lvds390pwrg4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn75lvdt386dgg active tssop dgg 64 25 tbd cu nipdau level-1-220c-unlim sn75lvdt386dggr active tssop dgg 64 2000 tbd cu nipdau level-1-220c-unlim sn75lvdt388adbt active sm8 dbt 38 50 tbd cu nipdau level-2-220c-1 year sn75lvdt388adbtg4 active sm8 dbt 38 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year sn75lvdt388adbtr active sm8 dbt 38 2000 tbd cu nipdau level-2-220c-1 year sn75lvdt388adbtrg4 preview sm8 dbt 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year sn75lvdt390d active soic d 16 40 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim sn75lvdt390dr active soic d 16 2500 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim package option addendum www.ti.com 18-mar-2005 addendum-page 1
orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) sn75lvdt390pw active tssop pw 16 90 tbd cu nipdau level-1-220c-unlim sn75lvdt390pwr active tssop pw 16 2000 tbd cu nipdau level-1-220c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 18-mar-2005 addendum-page 2
mechanical data mpds019d ? february 1996 ? revised february 2002 post office box 655303 ? dallas, texas 75265 dbt (r-pdso-g**) plastic small-outline package 30 pins shown 0,75 0,25 0,50 0,15 nom gage plane 50 12,60 38 9,80 11,10 44 12,40 9,60 10,90 4073252/e 02/02 4,30 4,50 0,27 0,17 16 15 30 a 1 6,60 24 dim a max pins ** 6,40 a min 1,20 max 6,60 6,20 seating plane 0,10 0,50 m 0,08 0 ? 8 5,10 20 4.90 0,15 0,05 7,90 30 7,70 7,90 28 7,70 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. falls within jedec mo-153

mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
mechanical data mtss003d january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 dgg (r-pdso-g**) plastic small-outline package 4040078 / f 12/97 48 pins shown 0,25 0,15 nom gage plane 6,00 6,20 8,30 7,90 0,75 0,50 seating plane 25 0,27 0,17 24 a 48 1 1,20 max m 0,08 0,10 0,50 0 8 56 14,10 13,90 48 dim a max a min pins ** 12,40 12,60 64 17,10 16,90 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold protrusion not to exceed 0,15. d. falls within jedec mo-153
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